The present invention relates to a dual polarity non-volatile MOS analog memory (MAM) cell.
There is currently a great deal of effort in implementing neural type networks in VLSI circuitry. Such implementation represents a practical way to realize the tremendous potential applications demonstrated in computer simulations.
A major part of any neural network is the weighting matrix, which stores the relative strengths of interconnections between processing units. Most useful applications require on the order of several thousand to several million weighting elements. In many networks these weights can be either excitatory (positive) or inhibitory (negative). In a learning network the weights must also be modifiable. Therefore, the ideal weighting element will have a long storage life time, be continuously adjustable, compact in size, and be able to store a positive or negative weight. Also, since many learning rules compute changes in weighting values, one would like to be able to update the weight in increments or decrements.
One type of non-volatile charge storing device is described in "FAMOS-A New Semiconductor Charge Storage Device," by Frohman-Bentchkowsky, D., Solid-State Electronics, Volume 17, pages 517-529, 1974. The structure of the device disclosed by this reference is a p-channel, silicon gate, field effect transistor in which no electric contact is made to the silicon gate. It combines the floating gate concept with avalanche injection of electrons from the surface depletion region of a p-n junction to yield reproducible charging characteristics with long term storage retention. FAMOS was intended to store digital weights and had to be erased by illumination with ultraviolet light.
Another device that provides non-volatile storage of data is described in "DIFMOS-A Floating-Gate Electrically Erasable Non-Volatile Semiconductor Memory Technology," by Gosney, W. M., IEEE Transactions on Electron Devices, Volume Ed-24, No. 5, May 1977. DIFMOS was intended to be used as digital device that provides an electrically alterable read only memory. The charge on the gate was limited only to non-positive values. DIFMOS also required a bootstrap capacitor with a 40 volt bias to erase charge on the gate.
A floating gate non-volatile memory device for storing analog information is described in "A Electrically Trainable Artificial Neural Network (ETANN) With 10240 Floating Gate Synapses," Holler, M., Tam, S., Castro, H., Benson, R., IJCNN International Joint Conference on Neural Networks, Vol. II, Washington D. C., pp. II-191 to II-196, 1989, published by the Institute of Electrical and Electronics Engineers, Inc., IEEE Catalog No. 89CH2765-6. This reference discloses a synapse cell circuit which is an NMOS version of a Gilbert-Multiplier. A pair of EEPROM cells are incorporated in which a differential voltage representing the weight may be stored or adjusted. Electrons are added to or removed from the floating gates of the EEPROM cells by Fowler-Nordheim tunneling. A desired differential floating gate voltage can be attained by monitoring the conductances of the respected EEPROM MOSFET's. This device uses a thin gate oxide which is difficult to fabricate, and can result in low production yields. The performance of this device is sensitive to thickness variations of the gate oxide which causes variations of writing characteristics between devices. Since the EEPROM uses a differential pair of devices to achieve positive and negative weights, the updating must be done by symmetrically adjusting both devices in the pair.
All of these devices are limited to storing only zero or negative charge on a floating gate. DIFMOS and FAMOS are digital devices that are not intended to store analog information. Although the ETANN synapse by INTEL can store analog information, it must be used in pairs of symmetrical synapses in order to achieve dual polarity outputs, making it difficult to change values stored in this device. Therefore, a need exists for a relatively simple non-volatile, dual polarity memory cell which can store analog information.